Details of workshops to be held at the 2017 International Conference on Field-Programmable Technology.
Workshop one. Intel: working with OpenCL
Date and time: Wednesday 13 December, 2.00 pm - 5.00 pm
Presenter: Israr Sheikh, FAE Manager, South Asia Pacific at Intel-PSG
This half-day workshop will cover the following topics:
- Leveraging Intel Hyperflex FPGA Architecture with Stratix 10
- Flexibility of the Intel EMIB interface and benefits for future devices
- High-Level Design Tools: Intel FPGA SDK for OpenCL.
Workshop two. BAMBU: An open-source framework for research in high-level synthesis
Date and time: Thursday 14 December, 9.00 pm - 5.30 pm
Presenters: Christian Pilato, Università della Svizzera italiana (USI); Fabrizio Ferrandi, Politecnico di Milano
This full-day tutorial presents BAMBU, an open-source framework for research in high-level synthesis. It leverages the GCC compiler to automatically generate hardware accelerators directly from C language.
BAMBU is modular and extensible with custom optimization and transformation passes. It features a novel memory architecture that supports a wide range of C constructs, minimizing the need for code rewriting.
In this tutorial, hardware designers will understand how to create and integrate efficient accelerators, while software designers will learn how to accelerate their applications with limited effort. We will thus present an overview of the high-level synthesis process, the tool and how it can be used to generate accelerators for several platforms (from embedded to high-performance architectures).
We will also present how to simulate and validate the accelerators generated with BAMBU.
Workshop three. Xilinx: PYNQ - Python productivity for Zynq
Date and time: Thursday 14 December, 9.00 pm - 5.00 pm
Presenter: Parimal Patel
PYNQ is an open-source framework that enables programmers who want to use embedded systems to exploit the capabilities of Xilinx Zynq All Programmable SoCs (APSoC). It allows users to exploit custom hardware in the programmable logic without having to use ASIC-style CAD tools.
Instead the APSoC is programmed in Python and the code is developed and tested directly on the embedded system. The programmable logic circuits are imported as hardware libraries and programmed through their APIs, in essentially the same way that software libraries are imported and programmed.
The framework combines four main elements: (1) the use of a high-level productivity language, Python in this case; (2) Python-callable hardware libraries based on FPGA overlays; (3) a web-based architecture incorporating the open-source Jupyter Notebook infrastructure served from Zynq's embedded processors; and (4) Jupyter Notebook's client-side, web apps.
The result is a web-centric programming environment that enables software programmers to work at higher levels of design abstraction and to re-use both software and hardware libraries.
This tutorial will give a hands-on introduction to PYNQ framework using the low cost PYNQ-Z1 board. It will feature the latest PYNQ release which includes an updated API, an optimized video pipeline, and a simplified way of integrating new hardware and drivers into PYNQ.
The new logictools overlay will be introduced which provides generation of Boolean functions, finite state machine and digital pattern generation from Python. The custom hardware can be used to control and monitor standard and proprietary interfaces for industrial applications, providing custom hardware capability to software programmers.
With hardware programmability from Python, and powerful visualization and analysis capabilities, the logictools overlay provides unique capability for teaching digital logic to both programmers and engineers.
The PYNQ overlay design methodology for creating new overlays and binding into the PYNQ framework will also be covered..
Workshop four. An introduction to open source digital design - EDA, IP and SoC
Date and time: Friday 15 December, 9.00 pm - 5.00 pm
Presenter: Julius Baxter
Description: The open source digital design ecosystem is rapidly expanding and evolving. Major developments in tools, flows and IP have lead to an increased amount of attention and participation within the community, so too consideration by industry.
Major open source SoC development projects have sprung up, and the likes of the RISC-V Foundation and their open source ISA have made the industry have a good hard think about the status quo. The FOSSi Foundation has been formed to help coalesce the community and address major questions such as open source IP licensing.
At the grassroots, the ever increasing affordability of commodity FPGA platforms has resulted in an uptick in people publishing collaborating on open source digital design projects.
Even just 5 years ago, while open source software had become a major thing, digital design was still far too niche and inaccessible to know where to begin.
This workshop will act as an introduction to the various open source digital design projects and resources that are currently available.
Participants will work through setting up, configuring, building and debugging a RISC-V-based SoC on a commodity FPGA board. Through this activity they will work with:
- open source IP databases, package managers and flows
- open source simulation and verification environments
- an open source multi-core RISC-V-based SoC design
- open source software development and debug tools
The SoC design will be based (subject to change) on the PULP IP released by the ETH Zurich/University of Bologna group. Tool flows such as FuseSoc, Icarus Verilog, Verilator, and cocotb for testbench creation will be demonstrated.