Course Title: Diagnose and rectify faults in digital controls systems

Part B: Course Detail

Teaching Period: Term2 2022

Course Code: EEET7512C

Course Title: Diagnose and rectify faults in digital controls systems

Important Information:

Please note that this course may have compulsory in-person attendance requirements for some teaching activities.
To participate in any RMIT course in-person activities or assessment, you will need to comply with RMIT vaccination requirements which are applicable during the duration of the course. This RMIT requirement includes being vaccinated against COVID-19 or holding a valid medical exemption.
Please read this RMIT Enrolment Procedure as it has important information regarding COVID vaccination and your study at RMIT: https://policies.rmit.edu.au/document/view.php?id=209.
Please read the Student website for additional requirements of in-person attendance: https://www.rmit.edu.au/covid/coming-to-campus

Please check your Canvas course shell closer to when the course starts to see if this course requires mandatory in-person attendance. The delivery method of the course might have to change quickly in response to changes in the local state/national directive regarding in-person course attendance.

School: 520T Future Technologies

Campus: City Campus

Program: C6120 - Advanced Diploma of Engineering Technology - Electrical

Course Contact: Munir Muniruzzaman

Course Contact Phone: +61399254415

Course Contact Email: Munir.Muniruzzaman@rmit.edu.au


Name and Contact Details of All Other Relevant Staff

Gita Pendharkar
Ph: +613 9925 4701
Email: gita.pendharkar@rmit.edu.au  

Mr Sukhvir Singh Judge
Ph: +61 3 9925 4470 Fax: +61 3 9925 4377
Email: sukhvir.judge@rmit.edu.au

Appointments by email

Nominal Hours: 60

Regardless of the mode of delivery, represent a guide to the relative teaching time and student effort required to successfully achieve a particular competency/module. This may include not only scheduled classes or workplace visits but also the amount of effort required to undertake, evaluate and complete all assessment requirements, including any non-classroom activities.

Pre-requisites and Co-requisites

Common Unit Group

UEECD0007 Apply work health and safety regulations, codes and practices in the workplace

UEECD0051 Use drawings, diagrams, schedules, standards, codes and specifications

and

UEECD0043 Solve problems in direct current circuits

or

UEECD0044 Solve problems in multiple path circuits

UEECD0046 Solve problems in single path circuits

Course Description

In this course you will gain the skills and knowledge required to diagnose and rectify faults in digital controls systems.


National Codes, Titles, Elements and Performance Criteria

National Element Code & Title:

UEEIC0018 Diagnose and rectify faults in digital controls systems

Element:

1 Prepare to diagnose and rectify faults

Performance Criteria:

1. 1

Work health and safety (WHS)/occupational health and safety (OHS) requirements and workplace procedures are identified and applied.

    

1.2 

Hazards are identified, risks are assessed and control measures implemented

    

1.3 

Safety hazards not previously identified are reported on job safety assessment and advice on risk control measures is sought from relevant person/s

    

1.4 

Extent of work is determined from reports, other documentation and discussions with appropriate person/s

    

1.5 

Appropriate person/s are consulted to ensure work is coordinated effectively with others

    

1.6 

Tools, equipment and testing devices required for diagnosing faults are obtained in accordance with workplace procedures and checked for correct operation and safety

    

Element:

2 Diagnose and rectify faults

Performance Criteria:

2.1 

WHS/OHS risk control measures and procedures for carrying out the work are followed

2.2 

Need to test or measure live electrical components is determined in accordance with workplace procedures

2.3 

Circuits/machines/plant are checked and isolated in accordance with workplace procedures

2.4 

Logical diagnostic methods are applied to diagnose electronic control system apparatus faults by employing measurements and estimations of system operating parameters

2.5 

Scenarios are tested as suspected cause of system faults

2.6 

Fault causes are identified and relevant person/s engaged where fault is outside scope of digital subsystems

2.7 

Faults in electronic components of control system are rectified

2.8 

System is tested and verified as operating to specified job requirements

2.9 

Unplanned situations are responded to in accordance with workplace procedures in a manner that minimises risk to personnel and equipment

2.10 

Methods for dealing with unplanned situations are selected based on safety and specified work outcomes

2.11 

Diagnosis and rectification work activities are performed using sustainable energy principles and practices without wasting materials, damaging apparatus, the surrounding environment or services

Element:

3 Complete and report fault diagnosis and rectification activities

Performance Criteria:

3.1 

WHS/OHS work completion risk control measures and workplace procedures are followed

3.2 

Worksite is made safe in accordance with workplace safety procedures

3.3 

Rectification of faults is documented in accordance with workplace procedures

3.4 

Relevant person/s is notified of system fault rectification in accordance with workplace procedures

Learning Outcomes


On successful completion of this course you will have developed and applied the skills and knowledge required to demonstrate competency in the above elements. 


Details of Learning Activities

You will involve in the following learning activities to meet requirement for this competency and stage 1 competencies for Engineering Associates.

  • Lectures 
      
  • Practicals
     
  • Projects


Engineers Australia Mapping Information:

This course is mapped against stage 1 competencies for Engineering Associates developed by Engineers Australia as detailed below:

EA 1. Knowledge and Skill Base

EA1.1. Descriptive, formula-based understanding of the underpinning natural and physical sciences and the engineering fundamentals applicable to the practice area.
EA 1.2. Procedural-level understanding of the mathematics, numerical analysis, statistics, and computer and information sciences which underpin the practice area.
EA 1.3. In depth practical knowledge and skills within specialist sub-disciplines of the practice area.
EA 1.4. Discernment of engineering developments within the practice area.
EA 1.5. Knowledge of contextual factors impacting the practice area.
EA 1.6. Understanding of the scope, principles, norms, accountabilities and bounds of contemporary engineering practice in the area of practice.

EA 2. Engineering Application Ability

EA 2.1. Application of established technical and practical methods to the solution of well-defined engineering problems.
EA 2.2. Application of technical and practical techniques, tools and resources to well defined engineering problems.
EA 2.3. Application of systematic synthesis and design processes to well defined engineering problems.
EA 2.4. Application of systematic project management processes.
 

EA 3. Professional and Personal Attributes

EA 3.1. Ethical conduct and professional accountability.
EA 3.2. Effective oral and written communication in professional and lay domains.
EA 3.3. Creative, innovative and pro-active demeanour.
EA 3.4. Professional use and management of information.
EA 3.5. Orderly management of self, and professional conduct.
EA 3.6. Effective team membership and team leadership.

Engineers Australia Stage 1 Competencies are mapped with competency UEENEEI139A in the Assessment Matrix.  


Teaching Schedule

The proposed teaching schedule for this competency is detailed below:

Week Topic Delivered Elements/Performance Criteria
1 Introduction to course, course guide, assessment, topics
breakdown, resources, OHS issues etc

UEEIC0018_1.1 

UEEIC0018_1.2 

UEEIC0018_1.3 

UEEIC0018_2.1 

UEEIC0018_3.1 

UEEIC0018_3.2 
2 Digital Systems & Number systems 

UEEIC0018_1.4 

UEEIC0018_1.5 

UEEIC0018_1.6 

UEEIC0018_2.4 

UEEIC0018_2.5 

UEEIC0018_2.8 

UEEIC0018_2.9 

UEEIC0018_2.10 
3

Logic gates, timing diagrams and interfacing between different logic families -

UEEIC0018_1.4 

UEEIC0018_1.5 

UEEIC0018_1.6 

UEEIC0018_2.4 

UEEIC0018_2.5 

UEEIC0018_2.6 

UEEIC0018_2.7 

UEEIC0018_2.8 

UEEIC0018_2.9 

UEEIC0018_2.10  

UEEIC0018_3.3 

UEEIC0018_3.4
4 Logic gates, timing diagrams and interfacing between different logic families
(continued)

Same as above
5 Combinational Logic -

 

UEEIC0018_1.4 

UEEIC0018_1.5 

UEEIC0018_1.6 

UEEIC0018_2.4 

UEEIC0018_2.5 

UEEIC0018_2.6 

UEEIC0018_2.7 

UEEIC0018_2.8 

UEEIC0018_2.9 

UEEIC0018_2.10  

UEEIC0018_3.3 

UEEIC0018_3.4 
6 Boolean Algebra and Logic simplification  & Encoders and Decoders 
 

UEEIC0018_1.4 

UEEIC0018_1.5 

UEEIC0018_1.6 

UEEIC0018_2.4 

UEEIC0018_2.5 

UEEIC0018_2.6 

UEEIC0018_2.7 

UEEIC0018_2.8 

UEEIC0018_2.9 

UEEIC0018_2.10  

UEEIC0018_3.3 

UEEIC0018_3.4 
7 Simplification using K-maps  & Flipflops 

UEEIC0018_1.4 

UEEIC0018_1.5 

UEEIC0018_1.6 

UEEIC0018_2.4 

UEEIC0018_2.5 

UEEIC0018_2.6 

UEEIC0018_2.7 

UEEIC0018_2.8 

UEEIC0018_2.9 

UEEIC0018_2.10  

UEEIC0018_3.3 

UEEIC0018_3.4 
8 Shift Registers & Counters

UEEIC0018_1.4 

UEEIC0018_1.5 

UEEIC0018_1.6 

UEEIC0018_2.4 

UEEIC0018_2.5 

UEEIC0018_2.6 

UEEIC0018_2.7 

UEEIC0018_2.8 

UEEIC0018_2.9 

UEEIC0018_2.10  

UEEIC0018_3.3 

UEEIC0018_3.4
9 DAC

UEEIC0018_1.4 

UEEIC0018_1.5 

UEEIC0018_1.6 

UEEIC0018_2.4 

UEEIC0018_2.5 

UEEIC0018_2.6 

UEEIC0018_2.7 

UEEIC0018_2.8 

UEEIC0018_2.9 

UEEIC0018_2.10  

UEEIC0018_3.3 

UEEIC0018_3.4 
10 ADC

UEEIC0018_1.4 

UEEIC0018_1.5 

UEEIC0018_1.6 

UEEIC0018_2.4 

UEEIC0018_2.5 

UEEIC0018_2.6 

UEEIC0018_2.7 

UEEIC0018_2.8 

UEEIC0018_2.9 

UEEIC0018_2.10  

UEEIC0018_3.3 

UEEIC0018_3.4 
11 Display devices 

UEEIC0018_1.4 

UEEIC0018_1.5 

UEEIC0018_1.6 

UEEIC0018_2.4 

UEEIC0018_2.5 

UEEIC0018_2.6 

UEEIC0018_2.7 

UEEIC0018_2.8 

UEEIC0018_2.9 

UEEIC0018_2.10  

UEEIC0018_3.3 

UEEIC0018_3.4 
12 Digital Fault Finding

UEEIC0018_1.4 

UEEIC0018_1.5 

UEEIC0018_1.6 

UEEIC0018_2.3 

 

UEEIC0018_2.4 

UEEIC0018_2.5 

UEEIC0018_2.6 

UEEIC0018_2.7 

UEEIC0018_2.8 

UEEIC0018_2.9 

UEEIC0018_2.10  

UEEIC0018_2.11  

UEEIC0018_3.3 

UEEIC0018_3.4 
13

Interfacing logic devices

UEEIC0018_1.4 

UEEIC0018_1.5 

UEEIC0018_1.6 

UEEIC0018_2.3 

UEEIC0018_2.4 

UEEIC0018_2.5 

UEEIC0018_2.6 

UEEIC0018_2.7 

UEEIC0018_2.8 

UEEIC0018_2.9 

UEEIC0018_2.10  

UEEIC0018_2.11  

UEEIC0018_3.3 

UEEIC0018_3.4 
14 PLD

UEEIC0018_1.4 

UEEIC0018_1.5 

UEEIC0018_1.6 

UEEIC0018_2.3 

UEEIC0018_2.4 

UEEIC0018_2.5 

UEEIC0018_2.6 

UEEIC0018_2.7 

UEEIC0018_2.8 

UEEIC0018_2.9 

UEEIC0018_2.10  

UEEIC0018_2.11  

UEEIC0018_3.3 

UEEIC0018_3.4 
15 System Testings and Diagnostic Methods 

UEEIC0018_1.4 

UEEIC0018_1.5 

UEEIC0018_1.6 

UEEIC0018_2.3 

UEEIC0018_2.4 

UEEIC0018_2.5 

UEEIC0018_2.6 

UEEIC0018_2.7 

UEEIC0018_2.8 

UEEIC0018_2.9 

UEEIC0018_2.10  

UEEIC0018_2.11  

UEEIC0018_3.3 

UEEIC0018_3.4 
16

Sustainable energy principles and practices 
 

Student project assessment

UEEIC0018_1.4 

UEEIC0018_1.5 

UEEIC0018_1.6 

UEEIC0018_2.3 

UEEIC0018_2.4 

UEEIC0018_2.5 

UEEIC0018_2.6 

UEEIC0018_2.7 

UEEIC0018_2.8 

UEEIC0018_2.9 

UEEIC0018_2.10  

UEEIC0018_2.11  

UEEIC0018_3.3 

UEEIC0018_3.4 
17-18 Assessment feedback, catch-up test, laboratory
work catch-up.

Final Exam 

UEEIC0018

: 1.1, 1,2, 1.3, 1.4, 1.5, 1.6, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 2.12, 2.11, 3.1, 3.2, 3.3, 3.4

Student directed hours involve completing activities such as reading online resources, assignments, individual student-teacher course-related consultation. Students are required to self-study the learning materials and complete the assigned out of class activities for the scheduled non-teaching hours. The estimated time is minimum 6 hours outside the class time.


Learning Resources

Prescribed Texts

Digital fundamentals by Thomas L. Floyd


References


Other Resources

Students will be able to access information and learning materials through myRMIT and may be provided with additional materials in class. List of relevant reference books, resources in the library and accessible Internet sites will be provided where possible. During the course, you will be directed to websites to enhance your knowledge and understanding of difficult concepts


Overview of Assessment

Assessment for this course is ongoing throughout the semester. Your knowledge and understanding of course content is assessed through participation in class exercises, oral/written presentations and through the application of learned skills and insights. Full assessment briefs will be provided and can be found on CANVAS.


Assessment Tasks

Assessment 1: Practical Test 1) (Week 5-8) & Practical Test 2: (Week 8-10)
Weighting towards final grade : 
The students will perform laboratories in groups which will be ongoing assessment.

Assessment 2: Project (Week 13-16)

A Digital project: - Students will be required to construct and test a project based on Digital Integrated Circuits and will be required to produce a project report. The project will commence on week 10 and students need to demonstrate the working project and submit the reports by week 17. The project details will be provided on the learning hub and student’s local drive.
 

Assessment 3: Theory Assessment: Test - (Week 17-18)

A closed book written Examination will be held on week 17-18 based on all the learning aspects of these competencies. 
 

Both the practical & theory assessment tasks need to be successfully completed to demonstrate competence.

To be deemed competent, student must achieve satisfactory (S) results in ALL assessments.

This course is assessed as Competent or Not Yet Competent and subsequently the following course results are allocated:

CA - Competency Achieved
NYC - Not Yet Competent
DNS - Did Not Submit for Assessment.

Assessment Due Dates

All assessment tasks will have a due date provided and published in Canvas. Assessments submitted after the due date will not be accepted unless an extension has been provided or special consideration has been granted.

  

Assessment Resubmissions (if Unsatisfactory)

You will be allowed 1 (ONE) resubmission attempt FOR EVERY ASSESSMENT (if unsatisfactory). You will be provided with a new due date by your teacher for your resubmission attempt if a resubmission is required.

 

If you do not submit your assessment (First attempt) by the due date you will not be eligible for resubmission if unsatisfactory.  

 


Assessment Matrix

Assessment vs UEEIC0018 Elements & Performance Criteria

Assessments 1.1 1.2 1.3 1.4 1.5 1.6 2.1 2.2 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.10 2.11 3.1 3.2 3.3 3.4
Laboratories & Practical tests  X X  X  X  X  X  X  X  X X  X  X  X  X X X X X X X   X X  X 
Project  X X  X  X  X  X  X  X  X  X  X  X  X  X X X X X X X  X  X  X 
Test              X X  X  X  X  X  X  X X X X X X X  X  X  X 

 Assessment vs Engineers Australia Stage 1 Competencies

Assessments EA1.1 EA1.2 EA1.3 EA1.4 EA1.5 EA1.6 EA2.1 EA2.2 EA2.3 EA2.4 EA3.1 EA3.2 EA3.13 EA3.4 EA3.5 EA3.6
Projects X X X X X X X X X X X X X X X X
Laboratories & Practical tests X X X X X X          X X  X  X  X  X 
Test X X X X X X X X X X            
ALL ASSESSMENTS (UEENEEI139A) 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2
0 (Blank) Graduate attribute is not assessed.
 
1 Graduate attribute is assessed in at least one, but less than one-third, of the Element
 
2 Graduate attribute is assessed in at least one third, but less than two-thirds, of the Element
 
3 Graduate attribute is assessed in more than two-thirds of the Element

 

Other Information

Credit Transfer and/or Recognition of Prior Learning (RPL):
You may be eligible for credit towards courses in your program if you have already met the learning/competency outcomes through previous learning and/or industry experience. To be eligible for credit towards a course, you must demonstrate that you have already completed learning and/or gained industry experience that is:
• Relevant
• Current
• Satisfies the learning/competency outcomes of the course
Please refer to http://www.rmit.edu.au/students/enrolment/credit to find more information about credit transfer and RPL
 

Study and learning Support:

Study and Learning Centre (SLC) provides free learning and academic development advice to all RMIT students.
Services offered by SLC to support numeracy and literacy skills of the students are:
- Assignment writing, thesis writing and study skills advice
- Maths and science developmental support and advice
- English language development

Please refer http://www.rmit.edu.au/studyandlearningcentre to find more information about Study and Learning Support.

Disability Liaison Unit:

If you have a long term medical condition and/or disability you can apply for adjustments to your study and assessment (Reasonable Adjustments and Equitable Assessment Arrangements) by registering with the Disability Liaison Unit (DLU) at http://www1.rmit.edu.au/browse;ID=01daxmpd1vo4z

Late submission:

Students requiring extensions for 7 calendar days or less (from the original due date) must complete and lodge an Application for Extension of Submittable Work (7 Calendar Days or less) form and lodge it with the Senior Educator/ Program Manager.
The application must be lodged no later than one working day before the official due date. The student will be notified within no more than 2 working days of the date of lodgment as to whether the extension has been granted.

Students seeking an extension of more than 7 calendar days (from the original due date) must lodge an Application for Special Consideration form under the provisions of the Special Consideration Policy, preferably prior to, but no later than 2 working days after the official due date.

Assignments submitted late without approval of an extension will not be accepted or marked.


Special consideration:

Please refer http://www.rmit.edu.au/browse;ID=riderwtscifm (unresolved)  to find more information about special consideration.

Plagiarism:

Plagiarism is a form of cheating and it is very serious academic offence that may lead to expulsion from the University.

Please refer: www.rmit.edu.au/academicintegrity to find more information about plagiarism.

Email Communication:

All email communications will be sent to your RMIT email address and you must regularly check your RMIT emails.

Course Overview: Access Course Overview